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isp1183 low-power universal serial bus interface device with dma rev. 01 24 february 2004 product data 1. general description the isp1183 is a universal serial bus (usb) interface device that complies with universal serial bus speci?cation rev. 2.0 , supporting data transfer at full-speed (12 mbit/s). it provides full-speed usb communication capacity to microcontroller or microprocessor-based systems. the isp1183 communicates with the systems microcontroller or microprocessor through a fast general-purpose parallel interface. the isp1183 supports fully autonomous, multicon?gurable direct memory access (dma) operation. the modular approach to implementing a usb interface device allows designer to select the optimum system microcontroller from the wide variety available. the ability to reuse existing architecture and ?rmware investments shortens development time, eliminates risks and reduces costs. the result is fast and ef?cient development of the most cost-effective usb peripheral solution. the isp1183 supports i/o voltage range of 1.65 v to 3.6 v enabling it to be directly interfaced to battery-operated devices, such as mobile phones. the isp1183 is ideally suited for battery-operated (low power) application in many portable peripherals such as mobile phones, personal digital assistants (pdas) and mp3 players. this device can be used in bus-powered or hybrid-powered applications. also, more number of endpoints in the isp1183 enable the device to be used in applications such as multifunctional printers, other than standard applications such as printers, communication devices, scanners, external mass storage devices and digital still cameras. 2. features n complies with universal serial bus speci?cation rev. 2.0 and most device class speci?cations n complies with acpi?, onnow? and usb power management requirements n supports data transfer at full-speed (12 mbit/s) n high performance usb interface device with integrated serial interface engine (sie), fifo memory, transceiver, and 3.3 v voltage regulator n high speed (11.1 mbyte/s or 90 ns read/write cycle) parallel interface n fully autonomous and multicon?guration dma operation n up to 14 programmable usb endpoints with 2 ?xed control in/out endpoints n integrated physical 2462 bytes of multicon?guration fifo memory n endpoints with double buffering to increase throughput and ease real-time data transfer n seamless interface with most microcontrollers and microprocessors
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 2 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. n bus-powered capability with low power consumption and low suspend current n software controlled connection to the usb bus (softconnect?) n supports internal power-on and low-voltage reset circuit n supports software reset n hybrid-powered capability with low-power consumption required from the system n v bus indication n 6 mhz crystal oscillator input with integrated pll for low emi n good usb connection indicator that blinks with traf?c (goodlink?) n supports i/o voltage range of 1.65 v to 3.6 v n operation over the extended usb bus voltage range (4.0 v to 5.5 v) with 3.3 v tolerant i/o pads n operating temperature range - 40 cto+85 c n full-scan design with high fault coverage n available in hvqfn32 lead-free and halogen-free package. 3. applications n battery-operated device, for example: u mobile phone u mp3 player u personal digital assistant (pda) n communication device, for example: u router u modem n digital camera n mass storage device, for example: u zip ? drive n printer n scanner. 4. abbreviations crc cyclic redundancy check dma direct memory access emi electromagnetic interference fifo first in, first out mmu memory management unit pid packet identi?er pio parallel i/o pll phase-locked loop sie serial interface engine usb universal serial bus.
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 3 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 5. ordering information table 1: ordering information type number package name description version ISP1183BS hvqfn32 plastic thermal enhanced very thin quad ?at package; no leads; 32 terminals; body 5 5 0.85 mm sot617-1
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x philips semiconductors isp1183 low-power usb interface device with dma 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 01 24 february 2004 4 of 62 6. block diagram fig 1. block diagram. 004aaa288 8 1.5 k w isp1183 bus interface analog tx/rx 3.3 v voltage regulator power-on reset memory management unit integrated ram micro controller handler endpoint handler 6 mhz xtal2 xtal1 to and from usb to and from microcontroller pll oscillator bit clock recovery philips sie softconnect int_n internal reset 3.3 v wr_n data[7:0] v bus dm dp v reg(3v3) agnd reset_n 1.65 v to 3.6 v level shifter pads suspend wakeup dma handler v dd(i/o) dgnd vbusdet_n dreq dack v dd 48 mhz 12 mhz 1 2 cs_n 3 rd_n 4 a0 17 5, 22, 25 67 8 9 10 11 12 13 15 14 16 18, 30 19, 20, 23, 24, 26 to 29 21 31 32
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 5 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7. pinning information 7.1 pinning 7.2 pin description fig 2. pin con?guration hvqfn32. 004aaa433 suspend wakeup data7 v dd(i/o) dgnd data5 data4 dm dp agnd v reg(3v3) dreq reset_n dack int_n cs_n wr_n rd_n a0 data2 data3 14 13 12 16 15 10 9 11 27 28 29 25 26 31 32 30 1 2 3 4 5 6 7 8 ISP1183BS v dd dgnd v dd(i/o) data6 data0 data1 vbusdet_n dgnd xtal1 xtal2 v bus 19 20 21 17 18 23 24 22 terminal 1 gnd (exposed die pad) bottom view table 2: pin description symbol [1] pin type description int_n 1 o interrupt output; active low 3.3 v tolerant i/o pad cs_n 2 i chip select input 3.3 v tolerant i/o pad wr_n 3 i write strobe input 3.3 v tolerant i/o pad rd_n 4 i read strobe input 3.3 v tolerant i/o pad dgnd 5 - digital ground supply xtal1 6 i crystal oscillator input (6 mhz); connect a fundamental parallel-resonant crystal or an external clock source (leave pin xtal2 unconnected) xtal2 7 o crystal oscillator output (6 mhz); connect a fundamental parallel-resonant crystal; leave this pin open when using an external clock source on pin xtal1
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 6 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. v bus 8iv bus sensing input and power supply input; see section 8.11 dm 9 ai/o usb d - line connection (analog) dp 10 ai/o usb d+ line connection (analog) agnd 11 - analog ground supply v reg(3v3) 12 - regulated supply voltage (3.3 v 10 %) from internal regulator; used to connect a 0.1 m f decoupling capacitor and pull-up resistor on pin dp remark: cannot be used to supply external devices. vbusdet_n 13 o v bus indicator output (active low); see ta b l e 3 dreq 14 o dma request output (4 ma; programmable polarity, see ta b l e 2 1 ); signals to the dma controller that the isp1183 wants to start a dma transfer 3.3 v tolerant i/o pad dack 15 i dma acknowledge input (programmable polarity, see ta b l e 2 1 ); used by the dma controller to signal the start of a dma transfer requested by the isp1183; when not in use, connect this pin to ground through a 10 k w resistor 3.3 v tolerant i/o pad reset_n 16 i reset input (schmitt trigger); a low level produces an asynchronous reset 3.3 v tolerant i/o pad a0 17 i address input; selects command (a0 = high) or data (a0 = low) 3.3 v tolerant i/o pad v dd(i/o) 18 - i/o power supply; add a decoupling capacitor of 0.1 m f (1.65 v to 3.6 v); see section 8.11 data0 19 i/o data bit 0 input and output bidirectional (4 ma), 3.3 v tolerant i/o pad data1 20 i/o data bit 1 input and output bidirectional (4 ma), 3.3 v tolerant i/o pad v dd 21 - 3.3 v output voltage; internally connected to the regulator output; connect to a decoupling capacitor of 0.1 m f dgnd 22 digital ground supply data2 23 i/o data bit 2 input and output bidirectional (4 ma), 3.3 v tolerant i/o pad data3 24 i/o data bit 3 input and output bidirectional (4 ma), 3.3 v tolerant i/o pad dgnd 25 - digital ground supply data4 26 i/o data bit 4 input and output bidirectional (4 ma), 3.3 v tolerant i/o pad data5 27 i/o data bit 5 input and output bidirectional (4 ma), 3.3 v tolerant i/o pad table 2: pin description continued symbol [1] pin type description
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 7 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] symbol names ending with underscore n (for example, name_n) represent active low signals. data6 28 i/o data bit 6 input and output bidirectional (4 ma), 3.3 v tolerant i/o pad data7 29 i/o data bit 7 input and output bidirectional (4 ma), 3.3 v tolerant i/o pad v dd(i/o) 30 - i/o power supply; add a decoupling capacitor of 0.1 m f wakeup 31 i wake-up input (edge triggered, low to high); generates a remote wake-up from the suspend state; when not in use, connect this pin to ground through a 10 k w resistor 3.3 v tolerant i/o pad suspend 32 o suspend state indicator output (4 ma) 3.3 v tolerant i/o pad gnd exposed die pad - ground supply; down bonded to the exposed die pad (heatsink); to be connected to the dgnd during pcb layout table 2: pin description continued symbol [1] pin type description
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 8 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8. functional description the isp1183 is a full-speed usb interface device with up to 14 con?gurable endpoints. it has a fast general-purpose parallel interface for communication with many types of microcontrollers and microprocessors. it supports an 8-bit data bus with separate address and data. the block diagram is given in figure 1 . the isp1183 has 2462 bytes of internal fifo memory that is shared among the enabled usb endpoints. the type and fifo size of each endpoint can be individually con?gured, depending on the required packet size. isochronous and bulk endpoints are double-buffered for increased data throughput. the isp1183 requires two supply voltages. the core voltage is supplied from v bus through an internal regulator, which transforms +5.0 v to +3.3 v when v bus is powered. the i/o interface voltage is supplied from v dd(i/o) , which can be 1.65 v to 3.6 v. the isp1183 operates on a 6 mhz oscillator frequency. 8.1 analog transceiver the transceiver is compliant with the universal serial bus speci?cation rev. 2.0 . it directly interfaces with the usb cable through external termination resistors. 8.2 philips sie the philips serial interface engine (sie) implements the full usb protocol layer. it is completely hardwired for speed and needs no ?rmware intervention. the functions of this block include: synchronization pattern recognition, parallel-to-serial conversion, bit (de)stuf?ng, crc checking and generation, packet identi?er (pid) veri?cation and generation, address recognition, and handshake evaluation and generation. 8.3 mmu and integrated ram the memory management unit (mmu) and the integrated ram provide the conversion between the usb speed (full-speed: 12 mbit/s bursts) and the parallel interface to the microcontroller (maximum 11.1 mbyte/s). this allows the microcontroller to read and write usb packets at its own speed. 8.4 softconnect the connection to usb is accomplished by pulling pin dp (for full-speed usb devices) high through a 1.5 k w pull-up resistor. in the isp1183, by default, the 1.5 k w pull-up resistor is integrated on-chip. the connection is established by a command sent from the external or system microcontroller. this allows the system microcontroller to complete its initialization sequence before deciding to establish connection with the usb. reinitialization of the usb connection can also be performed without disconnecting the cable. remark: the tolerance of the internal resistors is 25 %. this is higher than the 5 % tolerance speci?ed by the usb speci?cation. the overall voltage speci?cation for the connection, however, can still be met with a good margin. the decision to make use of this feature lies with the usb equipment designer.
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 9 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.5 bit clock recovery the bit clock recovery circuit recovers the clock from the incoming usb data stream using a 4 x oversampling principle. it can track jitter and frequency drift as speci?ed by the usb speci?cation rev. 2.0 . 8.6 voltage regulator a 5 v-to-3.3 v voltage regulator is integrated on-chip to supply the analog transceiver and internal logic. this voltage is available at pin v reg(3v3) to supply an external 1.5 k w pull-up resistor on pin dp. alternatively, the isp1183 provides softconnect technology through an integrated 1.5 k w pull-up resistor (see section 8.4 ). 8.7 pll clock multiplier a 6 mhz-to-48 mhz clock multiplier phase-locked loop (pll) is integrated on-chip. this allows for the use of a low-cost 6 mhz crystal, which also minimizes emi. no external components are required for the operation of the pll. 8.8 pio and dma interfaces a generic parallel i/o (pio) interface is de?ned for speed and ease-of-use. it also allows direct interfacing to most microcontrollers. to a microcontroller, the isp1183 appears as a memory device with an 8-bit data bus and a 1-bit address bus. the isp1183 supports nonmultiplexed address and data buses. the isp1183 can also be con?gured as a direct memory access (dma) slave device to allow more ef?cient data transfer. one of the 14 endpoint fifos may directly transfer data to or from the local shared memory. the dma interface can be independently con?gured from the pio interface. it can be directly interfaced to microprocessors or microcontrollers with i/o voltage range as low as 1.65 v. 8.9 v bus indicator the isp1183 indicates the availability of v bus using the v bus pin. when v bus is available (at pin v bus ), pin vbusdet_n will output low. when v bus is not available (at pin v bus ), pin vbusdet_n will output high. pin vbusdet_n will change from high-to-low level in approximately 2.5 ms to 3.5 ms. see section 19 . 8.10 operation modes the isp1183 can be operated in several operation modes as given in ta b l e 3 . table 3: isp1183 operation modes pin name plug-out state dead state reset state plug-in state normal state v bus 0vx 5v5v5v v dd(i/o) 1.8 v 0 v 1.8 v 1.8 v 1.8 v wakeup x x l l l reset_n x x l h h int_n h l [1] hh- [2]
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 10 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] not driven low. there is, however, no current ?ow through the pads because no i/o supply voltage is available. therefore, no potential will develop at the output. [2] during the normal operation, when v bus is available, pin suspend is low. if there is no activity on the usb bus for 3 ms or more, a suspend interrupt is generated on pin int_n. on receiving the suspend interrupt, the external processor issues a gosusp command to the device. once the gosusp command is issued by the processor, the device starts to prepare itself to go to the suspend mode. during suspend, to reduce power consumption, the internal clocks can be shut down. once the device is completely ready to go into the suspend mode, it will assert pin suspend high and go into the suspend mode. the typical time between the issuing of the gosusp command to the device and the device asserting pin suspend high is approximately 2 ms. [3] independent of the external reset. depends only on the power-on reset. [4] on connecting the usb cable (v bus ), pin vbusdet_n will change from high level to low level in approximately 2.5 ms to 3.5 ms. 8.11 power supply the isp1183 is powered from a single supply voltage, ranging from 4.0 v to 5.5 v. an integrated voltage regulator provides a 3.3 v supply voltage for the internal logic and the usb transceiver. this voltage is available at pin v reg(3v3) for connecting an external pull-up resistor on usb connection pin dp. see figure 3 . the isp1183 can also be operated from a 3.0 v to 3.6 v supply, as shown in figure 4 . in this case, the internal voltage regulator is disabled and pin v reg(3v3) must be connected to v bus . for details, see section 19 . 8.12 crystal oscillator the isp1183 has a crystal oscillator designed for a 6 mhz parallel-resonant crystal (fundamental). a typical circuit is shown in figure 5 . alternatively, an external clock signal of 6 mhz can be applied to input xtal1, while leaving output xtal2 open. suspend h l [1] lll vbusdet_n h l [1] l [3] h -> l [4] l data hi-z l [1] hi-z hi-z - table 3: isp1183 operation modes continued pin name plug-out state dead state reset state plug-in state normal state fig 3. isp1183 with a 4.0 v to 5.5 v supply. fig 4. isp1183 with a 3.0 v to 3.6 v supply. v bus v reg(3v3) v dd(i/o) isp1183 004aaa295 4.0 v to 5.5 v v dd(i/o) 1.65 v to 3.6 v v dd 8 12 18 30 21 3.0 v to 3.6 v 004aaa296 v bus v reg(3v3) v dd(i/o) isp1183 v dd(i/o) v dd 8 12 18 30 21
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 11 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. the 6 mhz oscillator frequency is multiplied to 48 mhz by an internal pll. in the suspend state, the crystal oscillator and the pll are switched off to save power. the oscillator operation is controlled by using bit clkrun in the hardware con?guration register. clkrun switches the oscillator on and off. 8.13 power-on reset the isp1183 has an internal power-on reset (por) circuit. the clock signal normally requires 3 ms to 4 ms to stabilize. the triggering voltage of the por circuit is 0.5 v nominal. a por is automatically generated when v dd(i/o) goes below the trigger voltage for a duration longer than 50 m s. fig 5. typical oscillator circuit. 6 mhz 18 pf 18 pf xtal2 xtal1 004aaa294 isp1183 6 7 t 1 : clock is running t 2 : registers are accessible fig 6. por timing. stable external clock available at a. fig 7. clock with respect to the external por. 004aaa390 t 1 t 2 v dd(i/o) 0.5 v 0 v 350 m s 2 ms por por external clock a 004aaa365
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 12 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. a hardware reset disables all usb endpoints and clears all endpoint con?guration registers (ecrs), except for the control endpoint that is ?xed and always enabled. section 10.3 explains how to (re)initialize endpoints. 9. interrupts figure 8 shows the interrupt logic of the isp1183. each of the indicated usb events is logged in a status bit of the interrupt register. corresponding bits in the interrupt enable register determine whether an event will generate an interrupt. interrupts can be masked globally using bit intena of the mode register (see ta b l e 1 8 ). the signaling mode of output int is controlled by bit intlvl of the hardware con?guration register (see ta b l e 2 0 ). default settings after reset is level mode. when pulse mode is selected, a pulse of 166 ns is generated when the or-ed combination of all interrupt bits changes from logic 0 to logic 1. bits suspnd, reset, resume, sp_eot, eot and sof are cleared when the interrupt register is read. the endpoint bits (ep0out to ep14) are cleared when the associated endpoint status register is read. bit bustatus follows the usb bus status exactly, allowing the ?rmware to get the current bus status when reading the interrupt register. fig 8. interrupt logic. 004aaa255 . . . ierst interrupt enable register iesusp ieresm iesof iep14 ... iep0in iep0out device mode register intena intlvl hardware configuration register pulse generator int 1 0 . . . . . . . . . interrupt register reset suspnd resume sof ep14 ... ep0in ep0out . . . . . . . . . . . . reset reset interrupt source suspend interrupt source epn interrupt source (clear epn interrupt; reading epn status register will set this signal) (clear suspend interrupt; reading interrupt register will set this signal) (clear reset interrupt; reading interrupt register will set this signal)
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 13 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. setup and out token interrupts are generated after the isp1183 has acknowledged the associated data packet. in the bulk transfer mode, the isp1183 will issue interrupts for every ack received for an out token or transmitted for an in token. in the isochronous mode, an interrupt is issued on each packet transaction. the ?rmware is responsible for timing synchronization with the host. this can be done using the pseudo start-of-frame (psof) interrupt, enabled using bit iepsof in the interrupt enable register. if a start-of-frame is lost, psof interrupts are generated every 1 ms. this allows the ?rmware to keep data transfer synchronized with the host. after three missed sof events, the isp1183 will enter the suspend state. an alternative way of handling the isochronous data transfer is to enable both the sof and psof interrupts and disable the interrupt for each isochronous endpoint.
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 14 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10. endpoint description each usb device is logically composed of several independent endpoints. an endpoint acts as a terminus of a communication ?ow between the host and the device. at design time, each endpoint is assigned a unique number (endpoint identi?er, see ta b l e 4 ). the combination of the device address (given by the host during enumeration), the endpoint number, and the transfer direction allows each endpoint to be uniquely referenced. the isp1183 has 16 endpoints: endpoint 0 (control in and out) plus 14 con?gurable endpoints, which can be individually de?ned as interrupt, bulk or isochronousin or out. each enabled endpoint has an associated fifo, which can be accessed either using the parallel i/o interface or dma. 10.1 endpoint access ta b l e 4 lists the endpoint access modes and programmability. all endpoints support i/o mode access. endpoints 1 to 14 also support dma access. fifo dma access is selected and enabled through bits epdix[3:0] and dmaen of the dma con?guration register. a detailed description of the dma operation is given in section 11 . [1] the total amount of fifo storage allocated to enabled endpoints must not exceed 2462 bytes. [2] in: input for the usb host (isp1183 transmits); out: output from the usb host (isp1183 receives). the data ?ow direction is determined by bit epdir in the endpoint con?guration register. 10.2 endpoint fifo size the fifo size determines the maximum packet size that the hardware can support for a given endpoint. only enabled endpoints are allocated space in the shared fifo storage, disabled endpoints have zero bytes. ta b l e 5 lists programmable fifo sizes. the following bits in the endpoint con?guration register (ecr) affect fifo allocation: ? endpoint enable bit (fifoen) ? size bits of an enabled endpoint (ffosz[3:0]) ? isochronous bit of an enabled endpoint (ffoiso). remark: register changes that affect the allocation of the shared fifo storage among endpoints must not be made while valid data is present in any fifo of the enabled endpoints. such changes will render all fifo contents unde?ned . table 4: endpoint access and programmability endpoint identi?er fifo size (bytes) [1] double buffering i/o mode access dma mode access endpoint type 0 64 (?xed) no yes no control out [2] 0 64 (?xed) no yes no control in [2] 1 to 14 programmable supported supported supported programmable
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 15 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. each programmable fifo can be independently con?gured through its ecr. the total physical size of all enabled endpoints (in plus out), however, must not exceed 2462 bytes. ta b l e 6 shows an example of a con?guration ?tting in the maximum available space of 2462 bytes. the total number of logical bytes in the example is 1311. the physical storage capacity used for double buffering is managed by the device hardware and is transparent to the user. table 5: programmable fifo size ffosz[3:0] nonisochronous isochronous 0000 8 bytes 16 bytes 0001 16 bytes 32 bytes 0010 32 bytes 48 bytes 0011 64 bytes 64 bytes 0100 reserved 96 bytes 0101 reserved 128 bytes 0110 reserved 160 bytes 0111 reserved 192 bytes 1000 reserved 256 bytes 1001 reserved 320 bytes 1010 reserved 384 bytes 1011 reserved 512 bytes 1100 reserved 640 bytes 1101 reserved 768 bytes 1110 reserved 896 bytes 1111 reserved 1023 bytes table 6: memory con?guration example physical size (bytes) logical size (bytes) endpoint description 64 64 control in (64-byte ?xed) 64 64 control out (64-byte ?xed) 2046 1023 double-buffered 1023-byte isochronous endpoint 16 16 16-byte interrupt out 16 16 16-byte interrupt in 128 64 double-buffered 64-byte bulk out 128 64 double-buffered 64-byte bulk in
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 16 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.3 endpoint initialization in response to the standard usb request set interface, the ?rmware must program all 16 ecrs of the isp1183 in sequence (see ta b l e 4 ), whether the endpoints are enabled or not. the hardware will then automatically allocate fifo storage space. if all endpoints have been successfully con?gured, the ?rmware must return an empty packet to the control in endpoint to acknowledge success to the host. if there are errors in the endpoint con?guration, the ?rmware must stall the control in endpoint. when reset by hardware or through the usb bus, the isp1183 disables all endpoints and clears all ecrs, except for the control endpoint, which is ?xed and always enabled. endpoint initialization can be done at any time. it is, however, valid only after enumeration. 10.4 endpoint i/o mode access when an endpoint event occurs (a packet is transmitted or received), the associated endpoint interrupt bits (epn) of the interrupt register (ir) are set by the sie. the ?rmware then responds to the interrupt and selects the endpoint for processing. the endpoint interrupt bit is cleared when the endpoint status register (esr) is read. the esr also contains information on the status of the endpoint buffer. for an out (= receive) endpoint, the packet length and the packet data can be read from the isp1183 by using the read buffer command. when the whole packet is read, the ?rmware sends a clear buffer command to enable the reception of new packets. for an in (= transmit) endpoint, the packet length and data to be sent can be written to the isp1183 by using the write buffer command. when the whole packet is written to the buffer, the ?rmware sends a validate buffer command to enable data transmission to the host. 10.5 special actions on control endpoints control endpoints require special ?rmware actions. the arrival of a setup packet ?ushes the in buffer and disables the validate buffer and clear buffer commands for the control in and out endpoints. the microcontroller needs to re-enable these commands by sending an acknowledge setup command to both control endpoints. this ensures that the last setup packet stays in the buffer and that no packets can be sent back to the host until the microcontroller has explicitly acknowledged that it has seen the setup packet.
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 17 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11. dma transfer direct memory access (dma) is a method to transfer data from one location to another in a computer system, without intervention of the central processor unit (cpu). many implementations of dma exist. the isp1183 supports two methods: ? 8237 compatible mode : based on the dma subsystem of the ibm ? personal computers (pc, at and all its successors and clones); this architecture uses the intel ? 8237 dma controller and has separate address spaces for memory and i/o ? dack-only mode : based on the dma implementation in some embedded risc processors, which has a single address space for both memory and i/o. the isp1183 supports dma transfer for all 14 con?gurable endpoints (see ta b l e 4 ). only one endpoint can be selected at a time for dma transfer. the dma operation of the isp1183 can be interleaved with normal i/o mode access to other endpoints. the following features are supported: ? single-cycle or burst transfers (up to 16 bytes per cycle) ? programmable transfer direction (read or write) ? programmable signal levels on pins dreq and dack. 11.1 selecting an endpoint for dma transfer the target endpoint for dma access is selected through bits epdix[3:0] in the dma con?guration register, see ta b l e 7 . the transfer direction (read or write) is automatically set by bit epdir in the associated ecr, to match the selected endpoint type (out endpoint: read; in endpoint: write). asserting input dack automatically selects the endpoint speci?ed in the dma con?guration register, regardless of the current endpoint used for i/o mode access. table 7: endpoint selection for dma transfer endpoint identi?er epdix[3:0] transfer direction epdir = 0 epdir = 1 1 0010 out: read in: write 2 0011 out: read in: write 3 0100 out: read in: write 4 0101 out: read in: write 5 0110 out: read in: write 6 0111 out: read in: write 7 1000 out: read in: write 8 1001 out: read in: write 9 1010 out: read in: write 10 1011 out: read in: write 11 1100 out: read in: write 12 1101 out: read in: write 13 1110 out: read in: write 14 1111 out: read in: write
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 18 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11.2 8237 compatible mode the 8237 compatible dma mode is selected by clearing bit dakoly in the hardware con?guration register (see ta b l e 2 0 ). the pin functions for this mode are shown in ta b l e 8 . the dma subsystem of an ibm-compatible pc is based on the intel 8237 dma controller. it operates as a ?y-by dma controller: the data is not stored in the dma controller, but it is transferred between an i/o port and a memory address. a typical example of the isp1183 in the 8237-compatible dma mode is given in figure 9 . the 8237 has two control signals for each dma channel: dreq (dma request) and dack_n (dma acknowledge). general control signals are hrq (hold request) and hlda (hold acknowledge). the bus operation is controlled using memr_n (memory read), memw_n (memory write), ior_n (i/o read) and iow_n (i/o write). table 8: 8237 compatible mode: pin functions symbol description i/o function dreq dma request o isp1183 requests a dma transfer dack dma acknowledge i dma controller con?rms the transfer rd_n read strobe i instructs the isp1183 to put data on the bus wr_n write strobe i instructs the isp1183 to get data from the bus fig 9. isp1183 in the 8237-compatible dma mode. data[7:0] cpu 004aaa291 ram isp1183 dma controller 8237 dreq dack dreq hrq hlda hrq hlda dack_n ior_n iow_n memr_n memw_n rd_n wr_n
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 19 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. the following example shows the steps that occur in a typical dma transfer: 1. the isp1183 receives a data packet in one of its endpoint fifos; the packet must be transferred to memory address 1234h. 2. the isp1183 asserts the dreq signal requesting the 8237 for a dma transfer. 3. the 8237 asks the cpu to release the bus by asserting the hrq signal. 4. after completing the current instruction cycle, the cpu places the bus control signals (memr_n, memw_n, ior_n and iow_n) and the address lines in three-state and asserts hlda to inform the 8237 that it has control of the bus. 5. the 8237 sets its address lines to 1234h and activates the memw_n and ior_n control signals. 6. the 8237 asserts dack_n to inform the isp1183 that it will start a dma transfer. 7. the isp1183 places the byte or word to be transferred on the data bus lines because its rd_n signal was asserted by the 8237. 8. the 8237 waits one dma clock period and then deasserts memw_n and ior_n. this latches and stores the byte or word at the desired memory location. it also informs the isp1183 that the data on the bus lines has been transferred. 9. the isp1183 deasserts the dreq signal to indicate to the 8237 that dma is no longer needed. in the single cycle mode this is done after each byte or word, in the burst mode following the last transferred byte or word of the dma cycle. 10. the 8237 deasserts the dack_n output indicating that the isp1183 must stop placing data on the bus. 11. the 8237 places the bus control signals (memr_n, memw_n, ior_n and iow_n) and the address lines in three-state and deasserts the hrq signal, informing the cpu that it has released the bus. 12. the cpu acknowledges control of the bus by deasserting hlda. after activating the bus control lines (memr_n, memw_n, ior_n and iow_n) and the address lines, the cpu resumes the execution of instructions. for a typical bulk transfer, the above process is repeated 64 times, once for each byte. after each byte, the address register in the dma controller is incremented and the byte counter is decremented. 11.3 dack-only mode the dack-only dma mode is selected by setting bit dakoly in the hardware con?guration register (see ta b l e 2 0 ). the pin functions for this mode are shown in ta b l e 9 . a typical example of the isp1183 in the dack-only dma mode is given in figure 10 . table 9: dack-only mode: pin functions symbol description i/o function dreq dma request o isp1183 requests a dma transfer dack dma acknowledge i dma controller con?rms the transfer; also functions as data strobe rd_n read strobe i not used wr_n write strobe i not used
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 20 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. in the dack-only mode, the isp1183 uses the dack signal as data strobe. input signals rd_n and wr_n are ignored. this mode is used in cpu systems that have a single address space for memory and i/o access. such systems have no separate memw_n and memr_n signals: the rd_n and wr_n signals are also used as memory data strobes. 11.4 end-of-transfer conditions 11.4.1 bulk endpoints a dma transfer to or from a bulk endpoint can be terminated by any of the following conditions (for bit names, refer to the dma con?guration register in ta b l e 3 2 ): ? the dma transfer completes as programmed in the dma counter register (cntren = 1) ? a short packet is received on an enabled out endpoint (shortp = 1) ? dma operation is disabled by clearing bit dmaen. dma counter register: an eot from the dma counter register is enabled by setting bit cntren in the dma con?guration register. the isp1183 has a 16-bit dma counter register, which speci?es the number of bytes to be transferred. when dma is enabled (dmaen = 1), the internal dma counter is loaded with the value from the dma counter register. when the internal counter completes the transfer as programmed in the dma counter, an eot condition is generated and the dma operation stops. short packet: normally, the transfer byte count must be set though a control endpoint before any dma transfer occurs. when a short packet has been enabled as eot indicator (shortp = 1), the transfer size is determined by the presence of a short packet in the data. this mechanism permits the use of a fully autonomous data transfer protocol. when reading from an out endpoint, reception of a short packet at an out token will stop the dma operation after transferring the data bytes of this packet. fig 10. isp1183 in the dack-only dma mode. ram isp1183 dma controller cpu dreq dack hrq hlda hrq hlda dreq_n dack_n rd_n wr_n 004aaa292 data[7:0]
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 21 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] the dma transfer stops. no interrupt, however, is generated. 11.4.2 isochronous endpoints a dma transfer to or from an isochronous endpoint can be terminated by any of the following conditions (for bit names refer to the dma con?guration register in ta b l e 3 2 ): ? the dma transfer completes as programmed in the dma counter register (cntren = 1) ? dma operation is disabled by clearing bit dmaen. table 10: summary of eot conditions for a bulk endpoint eot condition out endpoint in endpoint dma counter register transfer completes as programmed in the dma counter register transfer completes as programmed in the dma counter register short packet short packet is received and transferred counter reaches zero in the middle of the buffer dmaen bit in dma con?guration register dmaen = 0 [1] dmaen = 0 [1] table 11: recommended eot usage for isochronous endpoints eot condition out endpoint in endpoint dma counter register zero do not use preferred clear dmaen bit preferred do not use
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 22 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12. suspend and resume 12.1 suspend conditions the isp1183 detects a usb suspend status when a constant idle state is present on the usb bus for more than 3 ms. the bus-powered devices that are suspended must not consume more than 500 m a of current. this is achieved by shutting down power to system components or supplying them with a reduced voltage. the steps leading up to suspend status are as follows: 1. on detection of a wakeup-to-suspend transition, the isp1183 sets bit suspnd in the interrupt register. this will generate an interrupt if bit iesusp in the interrupt enable register is set. 2. when the ?rmware detects a suspend condition, it must prepare all system components for the suspend state: a. all signals connected to the isp1183 must enter appropriate states to meet the power consumption requirements of the suspend state. b. all input pins of the isp1183 must have a cmos low or high level. 3. in the interrupt service routine, the ?rmware must check the current status of the usb bus. when bit bustatus in the interrupt register is logic 0, the usb bus has left the suspend mode and the process must be aborted. otherwise, the next step can be executed. 4. to meet the suspend current requirements for a bus-powered device, the internal clocks must be switched off by clearing bit clkrun in the hardware con?guration register. 5. when the ?rmware has set and cleared bit gosusp in the mode register, the isp1183 enters the suspend state. in powered-off application, the isp1183 asserts output suspend and switches off the internal clocks after 2 ms. figure 11 shows a typical timing diagram.
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 23 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. in figure 11 : ? a : indicates the point at which the usb bus enters the idle state. ? b : indicates resume condition, which can be a 20 ms k-state on the usb bus, a high level on pin wakeup, or a low level on pin cs_n. ? c : indicates remote wake-up. the isp1183 will drive a k-state on the usb bus for 10 ms after pin wakeup goes high or pin cs_n goes low. ? d : after detecting the suspend interrupt, set and clear bit gosusp in the mode register. 12.1.1 powered-off application figure 12 shows a typical bus-powered modem application using the isp1183. the suspend output switches off power to the microcontroller and other external circuits during the suspend state. the isp1183 is woken up through the usb bus (global resume) or by the ring detection circuit on the telephone line. fig 11. suspend and resume timing. 004aaa359 int_n > 5 ms suspend interrupt usb bus gosusp wakeup suspend idle state 10 ms k-state > 3 ms 1.8 ms to 2.2 ms 0.5 ms to 3.5 ms resume interrupt a c d b fig 12. suspend and wakeup signals in a powered-off modem application. wakeup 8031 rst ring detection isp1183 dp dm usb v bus v bus v cc line 004aaa293 suspend
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 24 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12.2 resume conditions a wake-up from the suspend state is initiated either by the usb host or by the application: ? usb host : drives a k-state on the usb bus (global resume) ? application : remote wake-up through a high level on input wakeup or a low level on input cs_n (if enabled using bit wkupcs in the hardware con?guration register). wake-up on cs_n will work only if v bus is present. the steps of a wake-up sequence are as follows: 1. the internal oscillator and the pll multiplier are re-enabled. when stabilized, the clock signals are routed to all internal circuits of the isp1183. 2. the suspend output is deasserted, and bit resume in the interrupt register is set. this will generate an interrupt if bit ieresume in the interrupt enable register is set. 3. maximum 15 ms after starting the wake-up sequence, the isp1183 resumes its normal functionality. 4. in case of a remote wake-up, the isp1183 drives a k-state on the usb bus for 10 ms. 5. following the deassertion of output suspend, the application restores itself and other system components to the normal operating mode. 6. after wake-up, the internal registers of the isp1183 are write-protected to prevent corruption by inadvertent writing during power-up of external components. the ?rmware must send an unlock device command to the isp1183 to restore its full functionality. for more details, see section 13.4.2 . 12.3 control bits in suspend and resume table 12: summary of control bits register bit function interrupt suspnd a transition from awake to the suspend state was detected bustatus monitors usb bus status (logic 1 = suspend); used when interrupt is serviced resume a transition from suspend to the resume state was detected interrupt enable iesusp enables output int to signal the suspend state ieresume enables output int to signal the resume state mode softct enables softconnect pull-up resistor to usb bus gosusp a high-to-low transition enables the suspend state hardware con?guration extpul selects internal (softconnect) or external pull-up resistor wkupcs enables wake-up on low level of input cs_n pwroff selects powered-off mode during the suspend state unlock all sending data aa37h unlocks the internal registers for writing after a resume
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 25 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13. commands and registers the functions and registers of the isp1183 are accessed using commands, which consist of a command code followed by optional data bytes (read or write action). an overview of the available commands and registers is given in ta b l e 1 3 . a complete access consists of two phases: 1. command phase : when address pin a0 = high, the isp1183 interprets the data on the lower byte of the bus pins d[7:0] as a command code. commands without a data phase are immediately executed. 2. data phase (optional) : when address pin a0 = low, the isp1183 transfers the data on the bus to or from a register or endpoint fifo. multibyte registers are accessed least signi?cant byte or word ?rst. table 13: command and register summary name destination code (hex) transaction reference initialization commands write control out con?guration endpoint con?guration register endpoint 0 out 20 write 1 byte section 13.1.1 on page 27 write control in con?guration endpoint con?guration register endpoint 0 in 21 write 1 byte write endpoint n con?guration (n = 1 to 14) endpoint con?guration register endpoints 1 to 14 22 to 2f write 1 byte read control out con?guration endpoint con?guration register endpoint 0 out 30 read 1 byte read control in con?guration endpoint con?guration register endpoint 0 in 31 read 1 byte read endpoint n con?guration (n = 1 to 14) endpoint con?guration register endpoints 1 to 14 32 to 3f read 1 byte write or read device address address register b6/b7 write or read 1 byte section 13.1.2 on page 28 write or read mode register mode register b8/b9 write or read 1 byte section 13.1.3 on page 29 write or read hardware con?guration hardware con?guration register ba/bb write or read 2 bytes section 13.1.4 on page 29 write or read interrupt enable register interrupt enable register c2/c3 write or read 4 bytes section 13.1.5 on page 30 reset device resets all registers f6 - section 13.1.6 on page 32
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 26 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. data ?ow commands write control out buffer illegal: endpoint is read-only (00) - section 13.2.1 on page 32 write control in buffer fifo endpoint 0 in 01 n 64 bytes write endpoint n buffer (n = 1 to 14) fifo endpoints 1 to 14 (in endpoints only) 02 to 0f isochronous: n 1023 bytes interrupt or bulk: n 64 bytes read control out buffer fifo endpoint 0 out 10 n 64 bytes read control in buffer illegal: endpoint is write-only (11) - read endpoint n buffer (n = 1 to 14) fifo endpoints 1 to 14 (out endpoints only) 12 to 1f isochronous: n 1023 bytes interrupt or bulk: n 64 bytes stall control out endpoint endpoint 0 out 40 - section 13.2.3 on page 34 stall control in endpoint endpoint 0 in 41 - stall endpoint n (n = 1 to 14) endpoints 1 to 14 42 to 4f - read control out status endpoint status register endpoint 0 out 50 read 1 byte section 13.2.2 on page 33 read control in status endpoint status register endpoint 0 in 51 read 1 byte read endpoint n status (n = 1 to 14) endpoint status register n endpoints 1 to 14 52 to 5f read 1 byte validate control out buffer illegal: in endpoints only [1] (60) - section 13.2.4 on page 34 validate control in buffer fifo endpoint 0 in 61 - validate endpoint n buffer (n = 1 to 14) fifo endpoints 1 to 14 (in endpoints only) [1] 62 to 6f - clear control out buffer fifo endpoint 0 out 70 - section 13.2.5 on page 35 clear control in buffer illegal [2] (71) - clear endpoint n buffer (n = 1 to 14) fifo endpoints 1 to 14 (out endpoints only) [2] 72 to 7f - unstall control out endpoint endpoint 0 out 80 - section 13.2.3 on page 34 unstall control in endpoint endpoint 0 in 81 - unstall endpoint n (n = 1 to 14) endpoints 1 to 14 82 to 8f - check control out status [3] endpoint status image register endpoint 0 out d0 read 1 byte section 13.2.6 on page 35 check control in status [3] endpoint status image register endpoint 0 in d1 read 1 byte check endpoint n status (n = 1 to 14) [3] endpoint status image register n endpoints 1 to 14 d2 to df read 1 byte acknowledge setup endpoint 0 in and out f4 - section 13.2.7 on page 36 table 13: command and register summary continued name destination code (hex) transaction reference
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 27 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] validating an out endpoint buffer causes unpredictable behavior of the isp1183. [2] clearing an in endpoint buffer causes unpredictable behavior of the isp1183. [3] reads a copy of the status register: executing this command does not clear any status bits or interrupt bits. 13.1 initialization commands initialization commands are used during the enumeration process of the usb network. these commands are used to con?gure and enable the embedded endpoints. they also set the usb assigned address of the isp1183 and perform device reset. 13.1.1 endpoint con?guration register (r/w: 30hC3fh/20hC2fh) this command accesses the endpoint con?guration register (ecr) of the target endpoint. it de?nes the endpoint type (isochronous or bulk/interrupt), direction (out/in), fifo size and buffering scheme. it also enables the endpoint fifo. the register bit allocation is shown in ta b l e 1 4 . a bus reset will disable all endpoints. the allocation of fifo memory takes place only after all 16 endpoints have been con?gured in sequence (from endpoint 0 out to endpoint 14). although the control endpoints have ?xed con?gurations, they must be included in the initialization sequence and con?gured with their default values (see ta b l e 4 ). automatic fifo allocation starts when endpoint 14 is con?gured. remark: if any change is made to an endpoint con?guration that affects the allocated memory (size, enable/disable), the fifo memory contents of all endpoints become invalid. therefore, all valid data must be removed from enabled endpoints before changing the con?guration. code (hex): 20 to 2f write (control out, control in, endpoints 1 to 14) dma commands write or read dma function and scratch register dma function and scratch register b2/b3 write or read 2 bytes section 13.3.1 on page 36 write or read dma con?guration dma con?guration register f0/f1 write or read 2 bytes section 13.3.2 on page 37 write or read dma counter dma counter register f2/f3 write or read 2 bytes section 13.3.3 on page 38 general commands read control out error code error code register endpoint 0 out a0 read 1 byte section 13.4.1 on page 38 read control in error code error code register endpoint 0 in a1 read 1 byte read endpoint n error code (n = 1 to 14) error code register endpoints 1 to 14 a2 to af read 1 byte unlock device all registers with write access b0 write 2 bytes section 13.4.2 on page 39 read frame number frame number register b4 read 1 or 2 bytes section 13.4.3 on page 40 read chip id chip id register b5 read 2 bytes section 13.4.4 on page 41 read interrupt register interrupt register c0 read 4 bytes section 13.4.5 on page 41 table 13: command and register summary continued name destination code (hex) transaction reference
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 28 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. code (hex): 30 to 3f read (control out, control in, endpoints 1 to 14) transaction write or read 1 byte [1] the reset value of the control out endpoint is ?xed as 0x83 for the endpoint con?guration register. [2] the reset value of the control in endpoint is ?xed as 0xc3 for the endpoint con?guration register. 13.1.2 address register (r/w: b7h/b6h) this command sets the usb assigned address in the address register and enables the usb device. the address register bit allocation is shown in ta b l e 1 6 . a usb bus reset sets the device address to 00h (internally) and enables the device. the value of the address register (accessible by the microcontroller) is not altered by the bus reset. in response to the standard usb request (set address), the ?rmware must issue a write device address command, followed by sending an empty packet to the host. the new device address is activated when the host acknowledges the empty packet. code (hex): b6/b7 write or read address register transaction write or read 1 byte table 14: endpoint con?guration register: bit allocation bit 7 6 5 4 3 2 1 0 symbol fifoen epdir dblbuf ffoiso ffosz[3:0] reset [1][2] 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 15: endpoint con?guration register: bit description bit symbol description 7 fifoen logic 1 indicates an enabled fifo with allocated memory. logic 0 indicates a disabled fifo (no bytes allocated). 6 epdir this bit de?nes the endpoint direction (0 = out, 1 = in). it also determines the dma transfer direction (0 = read, 1 = write). 5 dblbuf logic 1 indicates that this endpoint has double buffering. 4 ffoiso logic 1 indicates an isochronous endpoint. logic 0 indicates a bulk or interrupt endpoint. 3 to 0 ffosz[3:0] this ?eld speci?es the fifo size according to ta b l e 5 . table 16: address register: bit allocation bit 7 6 5 4 3 2 1 0 symbol deven devadr[6:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 17: address register: bit description bit symbol description 7 deven logic 1 enables the device. 6 to 0 devadr[6:0] this ?eld speci?es the usb device address.
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 29 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.1.3 mode register (r/w: b9h/b8h) this command accesses the isp1183 mode register, which consists of 1 byte (bit allocation: see ta b l e 1 8 ). in the 16-bit bus mode, the upper byte is ignored. the mode register controls the dma bus width, resume and suspend modes, interrupt activity and softconnect operation. it can be used to enable debug mode, in which all errors and not acknowledge (nak) conditions will generate an interrupt. code (hex): b8/b9 write or read mode register transaction write or read 1 byte [1] unchanged by a bus reset. 13.1.4 hardware con?guration register (r/w: bbh/bah) this command accesses the hardware con?guration register that consists of 2 bytes. the ?rst (lower) byte contains the device con?guration and control values, the second (upper) byte holds the clock control bits and the clock division factor. the bit allocation is given in ta b l e 2 0 . a bus reset will not change any of the programmed bit values. the hardware con?guration register controls the connection to the usb bus, clock activity and power supply during the suspend state, output clock frequency, dma operating mode and pin con?gurations (polarity, signaling mode). code (hex): ba/bb write or read hardware con?guration register transaction write or read 2 bytes table 18: mode register: bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved reserved gosusp reserved intena dbgmod reserved softct reset 0 [1] 0000 [1] 0 [1] 0 [1] 0 [1] access r/w r/w r/w r/w r/w r/w r/w r/w table 19: mode register: bit description bit symbol description 7 reserved this bit should be always written as logic 0. 6 - reserved 5 gosusp writing logic 1 followed by logic 0 will activate the suspend mode. 4 - reserved 3 intena logic 1 enables all interrupts. bus reset value: unchanged. 2 dbgmod logic 1 enables the debug mode, in which all naks and errors will generate an interrupt. logic 0 selects normal operation, in which interrupts are generated on every ack (bulk endpoints) or after every data transfer (isochronous endpoints). bus reset value: unchanged. 1 - reserved 0 softct logic 1 enables softconnect (see section 8.4 ). this bit is ignored if extpul = 1 in the hardware con?guration register (see ta b l e 2 0 ). bus reset value: unchanged.
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 30 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.1.5 interrupt enable register (r/w: c3h/c2h) this command individually enables or disables interrupts from all endpoints, as well as interrupts caused by events on the usb bus (sof, sof lost, eot, suspend, resume, reset). a bus reset will not change any of the programmed bit values. the command accesses the interrupt enable register that consists of 4 bytes. the bit allocation is given in ta b l e 2 2 . table 20: hardware con?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved extpul reserved clkrun reserved reset 00100011 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dakoly drqpol dakpol reserved wkupcs reserved intlvl reserved reset 01000100 access r/w r/w r/w r/w r/w r/w r/w r/w table 21: hardware con?guration register: bit description bit symbol description 15 - reserved 14 extpul logic 1 indicates that an external 1.5 k w pull-up resistor is used on pin dp and that softconnect is not used. bus reset value: unchanged. 13 - reserved 12 clkrun logic 1 indicates that the internal clocks are always running, even during the suspend state. logic 0 switches off the internal oscillator and pll, when they are not needed. during the suspend state, this bit must be made logic 0 to meet the suspend current requirements. the clock is stopped after a delay of approximately 2 ms, following the setting of bit gosusp in the mode register. bus reset value: unchanged. 11 to 8 - reserved 7 dakoly logic 1 selects the dack-only dma mode. logic 0 selects the 8237 compatible dma mode. bus reset value: unchanged. 6 drqpol selects dreq signal polarity (0 = active low, 1 = active high). bus reset value: unchanged. 5 dakpol selects dack signal polarity (0 = active low, 1 = active high). bus reset value: unchanged. 4 reserved this bit should be always written as logic 0. 3 wkupcs logic 1 enables remote wake-up through a low level on input cs_n (for wake-up on cs_n to work, v bus must be present). bus reset value: unchanged. 2 - reserved 1 intlvl selects the interrupt signaling mode on output int (0 = level, 1 = pulsed). in the pulsed mode, an interrupt produces 166 ns pulse. for details, see section 12 . bus reset value: unchanged. 0 reserved this bit should be always written as logic 0.
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 31 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. code (hex): c2/c3 write or read interrupt enable register transaction write or read 4 bytes table 22: interrupt enable register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol iep14 iep13 iep12 iep11 iep10 iep9 iep8 iep7 reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol iep6 iep5 iep4 iep3 iep2 iep1 iep0in iep0out reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved sp_ieeot iepsof iesof ieeot iesusp ieresm ierst reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 23: interrupt enable register: bit description bit symbol description 31 to 24 - reserved; must write logic 0 23 iep14 logic 1 enables interrupts from endpoint 14. 22 iep13 logic 1 enables interrupts from endpoint 13. 21 iep12 logic 1 enables interrupts from endpoint 12. 20 iep11 logic 1 enables interrupts from endpoint 11. 19 iep10 logic 1 enables interrupts from endpoint 10. 18 iep9 logic 1 enables interrupts from endpoint 9. 17 iep8 logic 1 enables interrupts from endpoint 8. 16 iep7 logic 1 enables interrupts from endpoint 7. 15 iep6 logic 1 enables interrupts from endpoint 6. 14 iep5 logic 1 enables interrupts from endpoint 5. 13 iep4 logic 1 enables interrupts from endpoint 4. 12 iep3 logic 1 enables interrupts from endpoint 3. 11 iep2 logic 1 enables interrupts from endpoint 2. 10 iep1 logic 1 enables interrupts from endpoint 1. 9 iep0in logic 1 enables interrupts from the control in endpoint. 8 iep0out logic 1 enables interrupts from the control out endpoint. 7 - reserved 6 sp_ieeot logic 1 enables interrupt on detection of a short packet. 5 iepsof logic 1 enables 1 ms interrupts on detection of pseudo sof. 4 iesof logic 1 enables interrupt on sof detection.
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 32 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.1.6 reset device (f6h) this command resets the isp1183 in the same way as an external hardware reset through input reset_n. all registers are initialized to their reset values. code (hex): f6 reset the device transaction none 13.2 data ?ow commands data ?ow commands are used to manage the data transmission between usb endpoints and the system microcontroller. much of the data ?ow is initiated through an interrupt to the microcontroller. the data ?ow commands are used to access the endpoints and determine whether the endpoint fifos contain valid data. remark: the in buffer of an endpoint contains input data for the host. the out buffer receives output data from the host. 13.2.1 endpoint buffer (r/w: 10h, 12hC1fh/01hC0fh) this command accesses endpoint fifo buffers for reading or writing. first, the buffer pointer is reset to the beginning of the buffer. following the command, a maximum of (n + 2) bytes can be written or read, n representing the size of the endpoint buffer. after each read or write action, the buffer pointer is automatically incremented by one (8-bit bus width). in dma access, the ?rst two bytes (the packet length) are skipped: transfers start at the third byte of the endpoint buffer. when reading, the isp1183 can detect the last byte through the eop condition. when writing to a bulk or interrupt endpoint, the endpoint buffer must be completely ?lled before sending data to the host. remark: reading data after a write endpoint buffer command or writing data after a read endpoint buffer command data will cause unpredictable behavior of the isp1183. code (hex): 01 to 0f write (control in, endpoints 1 to 14) code (hex): 10, 12 to 1f read (control out, endpoints 1 to 14) transaction write or read maximum (n + 2) bytes (isochronous endpoint: n 1023, bulk or interrupt endpoint: n 64) the data in the endpoint fifo must be organized as shown in ta b l e 2 4 . examples of endpoint fifo access are given in ta b l e 2 5 . 3 ieeot logic 1 enables interrupt on eot detection. 2 iesusp logic 1 enables interrupt on detection of a suspend state. 1 ieresm logic 1 enables interrupt on detection of a resume state. 0 ierst logic 1 enables interrupt on detection of a bus reset. table 23: interrupt enable register: bit description continued bit symbol description
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 33 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. remark: there is no protection against writing or reading past a buffers boundary, against writing into an out buffer, or reading from an in buffer. any of these actions could cause an incorrect operation. data residing in an out buffer is meaningful only after a successful transaction. exception: during dma access of a double-buffered endpoint, the buffer pointer automatically points to the secondary buffer after reaching the end of the primary buffer. 13.2.2 endpoint status register (r: 50hC5fh) this command reads the status of an endpoint fifo. the command accesses the endpoint status register, the bit allocation of which is shown in ta b l e 2 6 . reading the endpoint status register will clear the interrupt bit set for the corresponding endpoint in the interrupt register (see ta b l e 4 6 ). all bits of the endpoint status register are read-only. bit epstal is controlled by the stall or unstall commands and by the reception of a setup token (see section 13.2.3 ). code (hex): 50 to 5f read (control out, control in, endpoints 1 to 14) transaction read 1 byte table 24: endpoint fifo organization byte # (8-bit bus) description 0 packet length (lower byte) 1 packet length (upper byte) 2 data byte 1 3 data byte 2 :: (n + 1) data byte n table 25: example of endpoint fifo access a0 phase bus lines byte # description high command d[7:0] - command code (00h to 1fh) low data d[7:0] 0 packet length (lower byte) low data d[7:0] 1 packet length (upper byte) low data d[7:0] 2 data byte 1 low data d[7:0] 3 data byte 2 low data d[7:0] 4 data byte 3 low data d[7:0] 5 data byte 4 ::::: table 26: endpoint status register: bit allocation bit 7 6 5 4 3 2 1 0 symbol epstal epfull1 epfull0 data_pid over write setupt cpubuf reserved reset 00000000 access rrrrrrrr
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 34 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.2.3 stall or unstall endpoint (40hC4fh/80hC8fh) these commands are used to stall or unstall an endpoint. the commands modify the content of the endpoint status register (see ta b l e 2 6 ). a stalled control endpoint is automatically unstalled when it receives a setup token, regardless of the packet content. if the endpoint should stay in its stalled state, the microcontroller can restall it with the stall endpoint command. when a stalled endpoint is unstalled (either by the unstall endpoint command or by receiving a setup token), it is also reinitialized. this ?ushes the buffer: if it is an out buffer, it waits for a data 0 pid; if it is an in buffer, it writes a data 0 pid. code (hex): 40 to 4f stall (control out, control in, endpoints 1 to 14) code (hex): 80 to 8f unstall (control out, control in, endpoints 1 to 14) transaction none remark: when unstalling a stalled endpoint, issue the unstall command two times. the ?rst unstall command will update the endpoint status register in ram. the second unstall command will reset the buffer pointers. 13.2.4 validate endpoint buffer (61hC6fh) this command signals the presence of valid data for transmission to the usb host, by setting the buffer full ?ag of the selected in endpoint. this indicates that the data in the buffer is valid and can be sent to the host, when the next in token is received. for a double-buffered endpoint, this command switches the current fifo for cpu access. table 27: endpoint status register: bit description bit symbol description 7 epstal this bit indicates whether the endpoint is stalled or not (1 = stalled, 0 = not stalled). set by a stall endpoint command. cleared by an unstall endpoint command. the endpoint is automatically unstalled on reception of a setup token. 6 epfull1 logic 1 indicates that the secondary endpoint buffer is full. 5 epfull0 logic 1 indicates that the primary endpoint buffer is full. 4 data_pid this bit indicates the data pid of the next packet (0 = data0 pid, 1 = data1 pid). 3 overwrite this bit is set by hardware. logic 1 indicates that a new setup packet has overwritten the previous setup information, before it was acknowledged or before the endpoint was stalled. this bit is cleared by reading, if writing the setup data has ?nished. firmware must check this bit before sending an acknowledge setup command or stalling the endpoint. on reading logic 1, the ?rmware must stop ongoing setup actions and wait for a new setup packet. 2 setupt logic 1 indicates that the buffer contains a setup packet. 1 cpubuf this bit indicates which buffer is currently selected for cpu access (0 = primary buffer, 1 = secondary buffer). 0 - reserved
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 35 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. remark: for special aspects of the control in endpoint, see section 10.5 . code (hex): 61 to 6f validate endpoint buffer (control in, endpoints 1 to 14) transaction none 13.2.5 clear endpoint buffer (70h, 72hC7fh) this command unlocks and clears the buffer of the selected out endpoint, allowing the reception of new packets. reception of a complete packet causes the buffer full ?ag of an out endpoint to be set. any subsequent packets are refused by returning a nak condition, until the buffer is unlocked using this command. for a double-buffered endpoint, this command switches the current fifo for cpu access. remark: for special aspects of the control out endpoint, see section 10.5 . code (hex): 70, 72 to 7f clear endpoint buffer (control out, endpoints 1 to 14) transaction none 13.2.6 check endpoint status (d0hCdfh) this command checks the status of the selected endpoint fifo without clearing any status or interrupt bits. the command accesses the endpoint status image register, which contains a copy of the endpoint status register. the bit allocation of the endpoint status image register is shown in ta b l e 2 8 . code (hex): d0 to df check status (control out, control in, endpoints 1 to 14) transaction write or read 1 byte table 28: endpoint status image register: bit allocation bit 7 6 5 4 3 2 1 0 symbol epstal epfull1 epfull0 data_pid over write setupt cpubuf reserved reset 00000000 access rrrrrrrr table 29: endpoint status image register: bit description bit symbol description 7 epstal this bit indicates whether the endpoint is stalled or not (1 = stalled, 0 = not stalled). 6 epfull1 logic 1 indicates that the secondary endpoint buffer is full. 5 epfull0 logic 1 indicates that the primary endpoint buffer is full. 4 data_pid this bit indicates the data pid of the next packet (0 = data0 pid, 1 = data1 pid).
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 36 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.2.7 acknowledge setup (f4h) this command acknowledges to the host that a setup packet was received. the arrival of a setup packet disables the validate buffer and clear buffer commands for the control in and out endpoints. the microcontroller needs to re-enable these commands by sending an acknowledge setup command, see section 10.5 . code (hex): f4 acknowledge setup transaction none 13.3 dma commands 13.3.1 dma function and scratch register (r/w: b3h/b2h) this command accesses the 16-bit dma function and scratch register, which can be used by the ?rmware to save and restore information. for example, the device status before powering down in the suspend state. the register bit allocation is given in ta b l e 3 0 . code (hex): b2/b3 write or read dma function and scratch register transaction write or read 2 bytes 3 overwrite this bit is set by hardware. logic 1 indicates that a new setup packet has overwritten the previous setup information, before it was acknowledged or before the endpoint was stalled. this bit is cleared by reading, if writing the setup data has ?nished. firmware must check this bit before sending an acknowledge setup command or stalling the endpoint. on reading logic 1, the ?rmware must stop ongoing setup actions and wait for a new setup packet. 2 setupt logic 1 indicates that the buffer contains a setup packet. 1 cpubuf this bit indicates which buffer is currently selected for cpu access (0 = primary buffer, 1 = secondary buffer). 0 - reserved table 29: endpoint status image register: bit description continued bit symbol description table 30: dma function and scratch register: bit allocation bit 15 14 13 12 11 10 9 8 symbol dmaen reserved sfirh[4:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol sfirl[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 37 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.3.2 dma con?guration register (r/w: f1h/f0h) this command de?nes the dma con?guration of the isp1183 and enables or disables dma transfers. the command accesses the dma con?guration register, which consists of 2 bytes. the bit allocation is given in ta b l e 3 2 . a bus reset will clear bit dmaen (dma disabled), all other bits remain unchanged. code (hex): f0/f1 write or read dma con?guration transaction write or read 2 bytes [1] unchanged by a bus reset. table 31: dma function and scratch register: bit description bit symbol description 15 dmaen writing logic 1 enables dma function. 14 to 13 - reserved; must be logic 0 12 to 8 sfirh[4:0] scratch information register (high byte) 7 to 0 sfirl[7:0] scratch information register (low byte) table 32: dma con?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol cntren shortp reserved reset 0 [1] 0 [1] 0 [1] 0 [1] 0 [1] 0 [1] 0 [1] 0 [1] access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol epdix[3:0] dma start reserved burstl[1:0] reset 0 [1] 0 [1] 0 [1] 0 [1] 000 [1] 0 [1] access r/w r/w r/w r/w r/w r/w r/w r/w table 33: dma con?guration register: bit description bit symbol description 15 cntren logic 1 enables the generation of an eot condition, when the dma counter register reaches zero. bus reset value: unchanged. 14 shortp logic 1 enables the short or empty packet mode. when receiving (out endpoint) a short or empty packet, an eot condition is generated. when transmitting (in endpoint), this bit should be cleared. bus reset value: unchanged. 13 to 8 - reserved 7 to 4 epdix[3:0] indicates the destination endpoint for dma, see ta b l e 7 .
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 38 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.3.3 dma counter register (r/w: f3h/f2h) this command accesses the dma counter register, which consists of 2 bytes. the bit allocation is given in ta b l e 3 4 . writing to the register sets the number of bytes for a dma transfer. reading the register returns the number of remaining bytes in the current transfer. a bus reset will not change the programmed bit values. the internal dma counter is automatically reloaded from the dma counter register when dma is re-enabled (dmaen = 1). for more details, see section 13.3.2 . code (hex): f2/f3 write or read dma counter register transaction write or read 2 bytes 13.4 general commands 13.4.1 endpoint error code (r: a0hCafh) this command returns the status of the last transaction of the selected endpoint, as stored in the error code register. each new transaction overwrites the previous status information. the bit allocation of the error code register is shown in ta b l e 3 6 . 3 dmastart writing logic 1 starts dma transfer. logic 0 forces the end of an ongoing dma transfer. reading this bit indicates whether dma is started (0 = dma stopped, 1 = dma started). this bit is cleared by a bus reset. 2 - reserved 1 to 0 burstl[1:0] selects the dma burst length: 00 single-cycle mode (1 byte) 01 burst mode (4 bytes) 10 burst mode (8 bytes) 11 burst mode (16 bytes). bus reset value: unchanged. table 33: dma con?guration register: bit description continued bit symbol description table 34: dma counter register: bit allocation bit 15 14 13 12 11 10 9 8 symbol dmacrh[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dmacrl[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 35: dma counter register: bit description bit symbol description 15 to 8 dmacrh[7:0] dma counter register (high byte) 7 to 0 dmacrl[7:0] dma counter register (low byte)
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 39 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. code (hex): a0 to af read error code (control out, control in, endpoints 1 to 14) transaction read 1 byte 13.4.2 unlock device (b0h) this command unlocks the isp1183 from write-protection mode after a resume. in the suspend state, all registers and fifos are write-protected to prevent data corruption by external devices during a resume. also, the register access for reading is possible only after the unlock device command is executed. table 36: error code register: bit allocation bit 7 6 5 4 3 2 1 0 symbol unread data01 reserved error[3:0] rtok reset 00000000 access rrrrrrrr table 37: error code register: bit description bit symbol description 7 unread logic 1 indicates that a new event occurred before the previous status was read. 6 data01 this bit indicates the pid type of the last successfully received or transmitted packet (0 = data0 pid, 1 = data1 pid). 5 - reserved 4 to 1 error[3:0] error code. for error description, see ta b l e 3 8 . 0 rtok logic 1 indicates that data was successfully received or transmitted. table 38: transaction error codes error code (binary) description 0000 no error 0001 pid encoding error; bits 7 to 4 are not the inverse of bits 3 to 0 0010 pid unknown; encoding is valid, but pid does not exist 0011 unexpected packet; packet is not of the expected type (token, data, or acknowledge), or is a setup token to a noncontrol endpoint 0100 token crc error 0101 data crc error 0110 timeout error 0111 babble error 1000 unexpected end-of-packet 1001 sent or received nak (not acknowledge) 1010 sent stall; a token was received, but the endpoint was stalled 1011 over?ow; the received packet was larger than the available buffer space 1100 sent empty packet (iso only) 1101 bit stuf?ng error 1110 sync error 1111 wrong (unexpected) toggle bit in data pid; data was ignored
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 40 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. after waking up from the suspend state, the ?rmware must unlock the registers and fifos using this command, by writing the unlock code (aa37h) into the lock register (8-bit bus: lower byte ?rst). the bit allocation of the lock register is given in ta b l e 3 9 . code (hex): b0 unlock the device transaction write 2 bytes (unlock code) 13.4.3 frame number register (r: b4h) this command returns the frame number of the last successfully received sof. it is followed by reading one or two bytes from the frame number register, containing the frame number (lower byte ?rst). the frame number register is shown in ta b l e 4 1 . remark: after a bus reset, the value of the frame number register is unde?ned. code (hex): b4 read frame number transaction read 1 or 2 bytes [1] reset value unde?ned after a bus reset. table 39: lock register: bit allocation bit 15 14 13 12 11 10 9 8 symbol unlockh[7:0] = aah reset 10101010 access wwwwwwww bit 7 6 5 4 3 2 1 0 symbol unlockl[7:0] = 37h reset 00110111 access wwwwwwww table 40: lock register: bit description bit symbol description 15 to 0 unlock[15:0] sending data aa37h unlocks the internal registers and fifos for writing, following a resume. table 41: frame number register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved sofrh[2:0] reset [1] 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol sofrl[7:0] reset [1] 00000000 access rrrrrrrr
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 41 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.4.4 chip id register (r: b5h) this command reads the chip identi?cation code and hardware version number. the ?rmware must check this information to determine the supported functions and features. this command accesses the chip id register, which is shown in ta b l e 4 4 . code (hex): b5 read chip id transaction read 2 bytes 13.4.5 interrupt register (r: c0h) this command indicates the sources of interrupts as stored in the 4-byte interrupt register. each individual endpoint has its own interrupt bit. the bit allocation of the interrupt register is shown in ta b l e 4 6 . bit bustatus veri?es the current bus status in the interrupt service routine. interrupts are enabled through the interrupt enable register, see section 13.1.5 . while reading the interrupt register, read all the 4 bytes completely. code (hex): c0 read interrupt register transaction read 4 bytes table 42: frame number register: bit description bit symbol description 15 to 11 - reserved 10 to 8 sofrh[2:0] sof frame number (upper byte) 7 to 0 sofrl[7:0] sof frame number (lower byte) table 43: example of frame number register access a0 phase bus lines byte # description high command d[7:0] - command code (b4h) low data d[7:0] 0 frame number (lower byte) low data d[7:0] 1 frame number (upper byte) table 44: chip id register: bit allocation bit 15 14 13 12 11 10 9 8 symbol chipidh[7:0] reset 82h access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol chipidl[7:0] reset 11h access rrrrrrrr table 45: chip id register: bit description bit symbol description 15 to 8 chipidh[7:0] chip id code (82h) 7 to 0 chipidl[7:0] silicon version (11h)
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 42 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] the reset value of this bit depends on the current usb bus status. if the bus is idle, the reset value will be 1. table 46: interrupt register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00000000 access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol ep14 ep13 ep12 ep11 ep10 ep9 ep8 ep7 reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol ep6 ep5 ep4 ep3 ep2 ep1 ep0in ep0out reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol bustatus sp_eot psof sof eot suspnd resume reset reset 0 [1] 0000000 access rrrrrrrr table 47: interrupt register: bit description bit symbol description 31 to 24 - reserved 23 ep14 logic 1 indicates the interrupt source: endpoint 14. 22 ep13 logic 1 indicates the interrupt source: endpoint 13. 21 ep12 logic 1 indicates the interrupt source: endpoint 12. 20 ep11 logic 1 indicates the interrupt source: endpoint 11. 19 ep10 logic 1 indicates the interrupt source: endpoint 10. 18 ep9 logic 1 indicates the interrupt source: endpoint 9. 17 ep8 logic 1 indicates the interrupt source: endpoint 8. 16 ep7 logic 1 indicates the interrupt source: endpoint 7. 15 ep6 logic 1 indicates the interrupt source: endpoint 6. 14 ep5 logic 1 indicates the interrupt source: endpoint 5. 13 ep4 logic 1 indicates the interrupt source: endpoint 4. 12 ep3 logic 1 indicates the interrupt source: endpoint 3. 11 ep2 logic 1 indicates the interrupt source: endpoint 2. 10 ep1 logic 1 indicates the interrupt source: endpoint 1. 9 ep0in logic 1 indicates the interrupt source: control in endpoint. 8 ep0out logic 1 indicates the interrupt source: control out endpoint. 7 bustatus it monitors the current usb bus status (0 = awake, 1 = suspend). 6 sp_eot logic 1 indicates that an eot interrupt has occurred for a short packet.
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 43 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 5 psof logic 1 indicates that an interrupt is issued every 1 ms because of the pseudo sof; after three missed sofs, suspend state is entered. 4 sof logic 1 indicates that a sof condition was detected. 3 eot logic 1 indicates that an internal eot condition was generated by the dma counter reaching zero. 2 suspnd logic 1 indicates that an awake to suspend change of state was detected on the usb bus. 1 resume logic 1 indicates that a resume state was detected. 0 reset logic 1 indicates that a bus reset condition was detected. table 47: interrupt register: bit description continued bit symbol description
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 44 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14. limiting values [1] equivalent to discharging a 100 pf capacitor through a 1.5 k w resistor (human body model). 15. recommended operating conditions table 48: absolute maximum ratings in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v bus supply voltage - 0.5 +6.0 v v dd(i/o) i/o supply voltage - 0.5 +4.6 v v i digital input voltage level - 0.5 v dd(i/o) + 0.5 v i lu latch-up current v i < 0 or v i >v bus - 100 ma v esd electrostatic discharge voltage i li <1 m a [1] - 2000 +2000 v t stg storage temperature - 60 +150 c p tot total power dissipation v bus = 5.5 v - 100 mw table 49: recommended operating conditions symbol parameter conditions min typ max unit v bus supply voltage with regulator 4.0 5.0 5.5 v v dd(i/o) i/o supply voltage 1.65 - 3.6 v v i input voltage 0 - v dd(i/o) v v o(i/o) output i/o voltage 0 - v dd(i/o) v v i(ai/o) input voltage on analog i/o pins dp and dm 0 - 3.6 v v o(od) open-drain output pull-up voltage 0 - v bus v t amb ambient temperature - 40 - +85 c
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 45 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 16. static characteristics [1] for 3.3 v operation, pin v reg(3v3) must be connected to pin v bus . [2] in the suspend mode, the minimum voltage is 2.7 v. [3] external loading is not included. table 50: static characteristics; supply pins v bus = 4.0 v to 5.5 v; v dd(i/o) = 1.65 v to 3.6 v; v gnd =0v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v reg(3v3) regulated supply voltage v bus = 4.0 v to 5.5 v [1][2] 3.0 3.3 3.6 v i cc operating supply current v bus = 5.0 v; t amb =25 c -19 -ma i cc(susp) suspend supply current v bus = 5.0 v; t amb =25 c [3] - - 250 m a i ref(static) v dd(i/o) static i/o supply current suspend or no v bus -- 10 m a i ref v dd(i/o) operating i/o supply current - - 3.5 ma table 51: static characteristics: digital pins v bus = 4.0 v to 5.5 v; v dd(i/o) = 1.65 v to 3.6 v; v gnd =0v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v il(i/o) low-level i/o input voltage - - 0.2v dd(i/o) v v ih(i/o) high-level i/o input voltage 0.7v dd(i/o) -- v v ol low-level i/o output voltage - - 0.22v dd(i/o) v v oh high-level i/o output voltage 0.8v dd(i/o) -- v i li input leakage current - 1-+1 m a c i input capacitance - - 10 pf z i input impedance 2 - - m w
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 46 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] dp is the usb positive data pin; dm is the usb negative data pin. [2] includes external resistors of 22 w 1 % on both dp and dm. [3] this voltage is available at pin v reg(3v3) . [4] in the suspend mode, the minimum voltage is 2.7 v. table 52: static characteristics: analog i/o pins dp and dm [1] v bus = 4.0 v to 5.5 v; v dd(i/o) = 1.65 v to 3.6 v; v gnd =0v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit input levels v di differential input sensitivity | v i(dp) - v i(dm) | 0.2 - - v v cm differential common mode voltage includes v di range 0.8 - 2.5 v v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v output levels v ol low-level output voltage r l = 1.5 k w to +3.6 v - - 0.3 v v oh high-level output voltage r l =15k w to ground 2.8 - 3.6 v leakage current i lz off-state leakage current - 10 - +10 m a capacitance c in transceiver capacitance pin to ground - - 20 pf resistance r pu pull-up resistance on dp softconnect = on 1 - 2 k w z drv driver output impedance steady-state drive [2] 29 - 44 w z inp input impedance 10 - - m w termination v term termination voltage for upstream port pull-up (r pu ) [3][4] 3.0 - 3.6 v
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 47 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 17. dynamic characteristics [1] dependent on the crystal oscillator start-up time. [1] test circuit: see figure 27 . [2] excluding the ?rst transition from idle state. [3] characterized only, not tested. limits guaranteed by design. table 53: dynamic characteristics v bus = 4.0 v to 5.5 v; v dd(i/o) = 1.65 v to 3.6 v; v gnd =0v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit reset t w(reset_n) pulse width on input reset_n crystal oscillator running 50 - - m s crystal oscillator stopped [1] -3-ms crystal oscillator f xtal crystal frequency - 6 - mhz table 54: dynamic characteristics: analog i/o pins dp and dm [1] v bus = 4.0 v to 5.5 v; v dd(i/o) = 1.65 v to 3.6 v; v gnd =0v; t amb = - 40 c to +85 c; c l = 50 pf; r pu = 1.5 k w on dp to v term ; unless otherwise speci?ed. symbol parameter conditions min typ max unit driver characteristics t fr rise time c l =50pf; 10 % to 90 % of | v oh - v ol | 4 - 20 ns t ff fall time c l =50pf; 90 % to 10 % of | v oh - v ol | 4 - 20 ns frfm differential rise/fall time matching (t fr /t ff ) [2] 90 - 111.11 % v crs output signal crossover voltage [2][3] 1.3 - 2.0 v data source timing t feopt source eop width [3] 160 - 175 ns t fdeop source differential data-to-eop transition skew [3] - 2 - +5 ns receiver timing t jr1 receiver data jitter tolerance for consecutive transitions [3] - 18.5 - +18.5 ns t jr2 receiver data jitter tolerance for paired transitions [3] - 9 - +9 ns t feopr receiver se0 width accepted as eop [3] 82--ns t fst width of se0 during differential transition rejected as eop [3] --14ns
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 48 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 18. timing 18.1 parallel i/o timing [1] the minimum value for the data ?ow commands (see ta b l e 1 3 ) is 180 ns. table 55: dynamic characteristics: parallel interface timing v bus =v reg(3v3) = 2.7 v to 3.9 v; v dd(i/o) = 1.8 v symbol parameter conditions min max unit read timing (see figure 13 ) t rhax address hold time after rd_n high c l =30pf 0 - ns t avrl address setup time before rd_n low 0- ns t rhdz data outputs high-impedance time after rd_n high 0- ns t rhsh chip deselect time after rd_n high - 2- ns t rhrl rd_n low after rd_n high 65 - ns t rlrh rd_n pulse width 25 - ns t slrl cs_n time before rd_n low 0 - ns t rldv data valid time after rd_n low - 20 ns t rc (t rhrl +t rlrh ) read cycle time 90 - ns write timing (see figure 14 ) t whax address hold time after wr_n high 1 - ns t avwl address setup time before wr_n low 0- ns t slwl cs_n time before wr_n low 0 - ns t wl (t whwl +t wlwh ) write cycle time [1] 90/180 - ns t wlwh wr_n pulse width 22 - ns t whwl wr_n low after wr_n high [1] 68/158 - ns t whsh chip deselect time after wr_n high 0 - ns t dvwh data setup time before wr_n high 2 - ns t whdz data hold time after wr_n high 1 - ns
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 49 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 18.2 access cycle timing (1) if required, cs_n can be kept permanently asserted. there is no need to deassert and assert in between the read and write cycles. fig 13. parallel interface read timing. 004aaa256 a0 t rhax t avrl t rlrh t rldv t rhrl (1) data rd_n cs_n t rhsh t slrl t rhdz (1) if required, cs_n can be kept permanently asserted. there is no need to deassert and assert in between the read and write cycles. fig 14. parallel interface write timing. 004aaa257 cs_n a0 data wr_n t whax t avwl t whdz t dvwh t wlwh t whsh t whwl (1) t slwl table 56: dynamic characteristics: access cycle timing v bus =v reg(3v3) = 2.7 v to 3.9 v; v dd(i/o) = 1.8 v symbol parameter conditions min max unit write command + write data (see figure 15 and figure 16 ) t cy(wc-wd) cycle time for write command, then write data c l =30pf [1] 100 - ns t cy(wd-wd) cycle time for write data 90 - ns t cy(wd-wc) cycle time for write data, then write command 90 - ns
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 50 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] the minimum value for the data ?ow commands (see ta b l e 1 3 ) is 180 ns. write command + read data (see figure 17 and figure 18 ) t cy(wc-rd) cycle time for write command, then read data [1] 100 - ns t cy(rd-rd) cycle time for read data 90 - ns t cy(rd-wc) cycle time for read data, then write command 90 - ns table 56: dynamic characteristics: access cycle timing continued v bus =v reg(3v3) = 2.7 v to 3.9 v; v dd(i/o) = 1.8 v symbol parameter conditions min max unit fig 15. write command + write data cycle timing. (1) example: read data. fig 16. write data + write command cycle timing. fig 17. write command + read data cycle timing. 004aaa425 t cy(wc-wd) t cy(wd-wd) command data wr_n data data cs_n 004aaa426 t cy(wd-wc) data data wr_n data command rd_n cs_n (1) 004aaa427 t cy(wc-rd) t cy(rd-rd) command data wr_n data data rd_n cs_n
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 51 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 18.3 dma timing: single-cycle mode (1) example: read data. fig 18. read data + write command cycle timing. 004aaa428 t cy(rd-wc) data data wr_n data (1) command rd_n cs_n table 57: dynamic characteristics: single-cycle dma timing v bus =v reg(3v3) = 2.7 v to 3.9 v; v dd(i/o) = 1.8 v symbol parameter conditions min max unit 8237 compatible mode (see figure 19 ) t asrp dreq off after dack on - 40 ns t cy(dreq) cycle time signal dreq 90 - ns read in dack-only mode (see figure 20 ) t asrp dreq off after dack on - 40 ns t asap dack pulse width 25 - ns t asap +t aprs dreq on after dack off 90 - ns t asdv data valid after dack on - 22 ns t apdz data hold after dack off - 3 ns write in dack-only mode (see figure 21 ) t asrp dreq off after dack on - 40 ns t asap +t aprs dreq on after dack off 90 - ns t dvap data setup before dack off 5 - ns t apdz data hold after dack off 3 - ns fig 19. dma timing in 8237 compatible mode. 004aaa429 dreq dack_n t asrp t cy(dreq)
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 52 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 18.4 dma timing: burst mode fig 20. dma read timing in dack-only mode. 004aaa430 dack_n dreq t asrp t aprs t asdv t apdz data t asap fig 21. dma write timing in dack-only mode. 004aaa431 dack_n dreq t asrp t aprs t dvap t apdz data t asap table 58: dynamic characteristics: burst mode dma timing v bus =v reg(3v3) = 2.7 v to 3.9 v; v dd(i/o) = 1.8 v symbol parameter conditions min max unit burst (see figure 22 ) t rsih input rd_n or wr_n high after dreq on 22 - ns t ilrp dreq off after input rd_n or wr_n low -60ns t ihap dack off after input rd_n or wr_n high 0- ns t ihil dma burst repeat interval (input rd_n or wr_n high to low) 90 - ns
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 53 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 19. application information 19.1 bus-powered mode in the bus-powered mode, pin vbusdet_n is not necessary. see figure 23 . 19.2 hybrid-powered mode in this mode: ? when the usb cable is pulled out, pin vbusdet_n goes high, thereby indicating to the mcu that usb is disconnected. see figure 24 . ? when the usb cable is plugged in, pin vbusdet_n goes low. this indicates to the mcu that the usb cable is plugged in. the mcu can then prepare to recon?gure all registers of the isp1183. see figure 24 . fig 22. burst mode dma timing. 004aaa432 dack_n dreq t rsih t ilrp t ihil t ihap rd_n, wr_n fig 23. bus-powered mode. 004aaa451 mcu isp1183 v bus v reg(3v3) v dd(i/o) regulator v bus 1.65 v to 3.6 v v dd(i/o) 8 12 18 30 v cc
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 54 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 19.3 self-powered mode in the self-powered mode, pin vbusdet_n cannot be used. the v bus sensing can be done in the following two ways: ? connecting v bus to the mcu; see figure 25 . C when vbusdet goes low, the mcu clears bit softct. C when vbusdet goes high, the mcu sets bit softct. ? connecting transistor switching; see figure 26 . C when v bus is high, v reg(3v3) will bypass to pull up dp. this indicates that the device is connected. C when v bus is low, pull up dp is switched off. this indicates that the device is disconnected. remark: the above implementation is necessary to comply with usb-if requirements. fig 24. hybrid-powered mode. 004aaa452 mcu isp1183 v bus v reg(3v3) v dd(i/o) vbusdet_n v bus v dd(i/o) 8 12 18 30 v cc self-powered 13 self-powered (1.65 v to 3.6 v)
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 55 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 25. v bus connected to mcu. 004aaa454 mcu isp1183 vbusdet v cc self-powered dp dm 100 k w (3 v or 5 v) v bus 22 w 22 w v bus v reg(3v3) v dd(i/o) v dd(i/o) 8 12 18 30 self-powered (1.65 v to 3.6 v) dp dm fig 26. transistor switching. 004aaa453 mcu isp1183 v bus v reg(3v3) v dd(i/o) vbusdet v dd(i/o) 8 12 18 30 v cc self-powered dp dm v reg(3v3) 100 k w 22 k w 1.5 k w (3 v or 5 v) v bus 22 w 22 w self-powered (1.65 v to 3.6 v) dp dm
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 56 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20. test information the dynamic characteristics of the analog i/o ports (dp and dm ) as listed in ta b l e 5 4 were determined using the circuit shown in figure 27 . load capacitance: c l = 50 pf (full-speed mode) speed: full-speed mode only: internal 1.5 k w pull-up resistor on dp fig 27. load impedance for the dp and dm pins. test point c l 50 pf 22 w 15 k w d.u.t mgs784
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 57 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 21. package outline fig 28. hvqfn32 package outline. 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 5.1 4.9 d h 3.25 2.95 y 1 5.1 4.9 3.25 2.95 e 1 3.5 e 2 3.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot617-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot617-1 hvqfn32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 916 32 25 24 17 8 1 x d e c b a e 2 terminal 1 index area terminal 1 index area 01-08-08 02-10-18 1/2 e 1/2 e a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 58 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. 22. soldering 22.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. in these situations re?ow soldering is recommended. 22.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 22.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 59 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 22.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 22.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . table 59: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5][6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
philips semiconductors isp1183 low-power usb interface device with dma product data rev. 01 24 february 2004 60 of 62 9397 750 11804 ? koninklijke philips electronics n.v. 2004. all rights reserved. [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vsop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 23. revision history table 60: revision history rev date cpcn description 01 20040224 - product data (9397 750 11804)
9397 750 11804 philips semiconductors isp1183 low-power usb interface device with dma ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 01 24 february 2004 61 of 62 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 24. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 25. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 26. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 27. trademarks acpi is an open industry speci?cation for pc power management, co-developed by intel corp., microsoft corp. and toshiba goodlink is a trademark of koninklijke philips electronics n.v. ibm is a registered trademark of internal machines corp. intel is a registered trademark of intel corp. onnow is a trademark of microsoft corp. softconnect is a trademark of koninklijke philips electronics n.v. zip is a registered trademark of iomega corp. level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2004. printed in the netherlands all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 24 february 2004 document order number: 9397 750 11804 contents philips semiconductors isp1183 low-power usb interface device with dma 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 functional description . . . . . . . . . . . . . . . . . . . . . . . . 8 8.1 analog transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2 philips sie . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.3 mmu and integrated ram . . . . . . . . . . . . . . . . . . . . . 8 8.4 softconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.5 bit clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.6 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.7 pll clock multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.8 pio and dma interfaces . . . . . . . . . . . . . . . . . . . . . . 9 8.9 v bus indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.10 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.11 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.12 crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.13 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 10 endpoint description. . . . . . . . . . . . . . . . . . . . . . . . . 14 10.1 endpoint access. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 10.2 endpoint fifo size . . . . . . . . . . . . . . . . . . . . . . . . . 14 10.3 endpoint initialization . . . . . . . . . . . . . . . . . . . . . . . . 16 10.4 endpoint i/o mode access . . . . . . . . . . . . . . . . . . . . 16 10.5 special actions on control endpoints . . . . . . . . . . . . 16 11 dma transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11.1 selecting an endpoint for dma transfer . . . . . . . . . . 17 11.2 8237 compatible mode. . . . . . . . . . . . . . . . . . . . . . . 18 11.3 dack-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11.4 end-of-transfer conditions. . . . . . . . . . . . . . . . . . . . 20 11.4.1 bulk endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11.4.2 isochronous endpoints . . . . . . . . . . . . . . . . . . . . . . . 21 12 suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . 22 12.1 suspend conditions . . . . . . . . . . . . . . . . . . . . . . . . . 22 12.1.1 powered-off application . . . . . . . . . . . . . . . . . . . . . . 23 12.2 resume conditions. . . . . . . . . . . . . . . . . . . . . . . . . . 24 12.3 control bits in suspend and resume. . . . . . . . . . . . . 24 13 commands and registers . . . . . . . . . . . . . . . . . . . . . 25 13.1 initialization commands . . . . . . . . . . . . . . . . . . . . . . 27 13.1.1 endpoint con?guration register (r/w: 30hC3fh/20hC2fh) . . . . . . . . . . . . . . . . . . . 27 13.1.2 address register (r/w: b7h/b6h) . . . . . . . . . . . . . . 28 13.1.3 mode register (r/w: b9h/b8h) . . . . . . . . . . . . . . . . 29 13.1.4 hardware con?guration register (r/w: bbh/bah) . 29 13.1.5 interrupt enable register (r/w: c3h/c2h). . . . . . . . 30 13.1.6 reset device (f6h) . . . . . . . . . . . . . . . . . . . . . . . . . 32 13.2 data ?ow commands . . . . . . . . . . . . . . . . . . . . . . . . 32 13.2.1 endpoint buffer (r/w: 10h, 12hC1fh/01hC0fh) . . 32 13.2.2 endpoint status register (r: 50hC5fh) . . . . . . . . . . 33 13.2.3 stall or unstall endpoint (40hC4fh/80hC8fh) . . . . 34 13.2.4 validate endpoint buffer (61hC6fh). . . . . . . . . . . . . 34 13.2.5 clear endpoint buffer (70h, 72hC7fh) . . . . . . . . . . 35 13.2.6 check endpoint status (d0hCdfh) . . . . . . . . . . . . . 35 13.2.7 acknowledge setup (f4h) . . . . . . . . . . . . . . . . . . . . 36 13.3 dma commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 13.3.1 dma function and scratch register (r/w: b3h/b2h) 36 13.3.2 dma con?guration register (r/w: f1h/f0h) . . . . . . 37 13.3.3 dma counter register (r/w: f3h/f2h) . . . . . . . . . . 38 13.4 general commands . . . . . . . . . . . . . . . . . . . . . . . . . 38 13.4.1 endpoint error code (r: a0hCafh) . . . . . . . . . . . . 38 13.4.2 unlock device (b0h). . . . . . . . . . . . . . . . . . . . . . . . . 39 13.4.3 frame number register (r: b4h) . . . . . . . . . . . . . . . 40 13.4.4 chip id register (r: b5h) . . . . . . . . . . . . . . . . . . . . . 41 13.4.5 interrupt register (r: c0h) . . . . . . . . . . . . . . . . . . . . 41 14 limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 15 recommended operating conditions . . . . . . . . . . . . 44 16 static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 45 17 dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 47 18 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 18.1 parallel i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 18.2 access cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . 49 18.3 dma timing: single-cycle mode . . . . . . . . . . . . . . . . 51 18.4 dma timing: burst mode . . . . . . . . . . . . . . . . . . . . . . 52 19 application information . . . . . . . . . . . . . . . . . . . . . . . 53 19.1 bus-powered mode. . . . . . . . . . . . . . . . . . . . . . . . . . 53 19.2 hybrid-powered mode . . . . . . . . . . . . . . . . . . . . . . . 53 19.3 self-powered mode. . . . . . . . . . . . . . . . . . . . . . . . . . 54 20 test information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 21 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 22 soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 22.1 introduction to soldering surface mount packages . . 58 22.2 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 22.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 22.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 22.5 package related soldering information . . . . . . . . . . . 59 23 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 24 data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 25 de?nitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 26 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 27 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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